1. Field
This disclosure relates to fabrication of semiconductor structures on substrates. More specifically, the present disclosure describes methods for growing semiconductor structures on substrates and reusing the substrates.
2. Description of Related Art
The following commonly assigned and copending applications describe the growth of vertically aligned Si wire arrays on a substrate: “U.S. Patent Application No. 60/961,170, titled “Fabrication of Wire Array Samples and Controls,” filed on Jul. 19, 2007; U.S. Patent Application No. 60/961,169, titled “Growth of Vertically Aligned Si Wire Arrays Over Large Areas (>1 cm2) with Au and Cu Catalysts,” filed on Jul. 19, 2007. These methods to grow high quality, vertically aligned arrays of Si wires may require an expensive, single crystal Si (111) wafer to be used as a substrate. This may hinder the potential of these wire arrays to be used as part of a cheaper alternative to traditional, planar junction solar cells.